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TMS320C5515
SPRS645F – AUGUST 2010 – REVISED OCTOBER 2013
www.ti.com
3.7.1.3
MMC0, I2S0, and GP[5:0] Pin Multiplexing [EBSR.SP0MODE Bits]
The MMC0, I2S0, and GPIO signal muxing is determined by the value of the SP0MODE bit fields in the
External Bus Selection Register (EBSR) register. For more details on the actual pin functions, see
Table 3-8 .
Table 3-8. MMC0, I2S0, and GP[5:0] Pin Multiplexing
EBSR SP0MODE BITS
PDINHIBR1
REGISTER
BIT FIELDS (1)
S00PD
S01PD
S02PD
S03PD
S04PD
S05PD
PIN NAME
MMC0_CLK/I2S0_CLK/GP[0]
MMC0_CMD/I2S0_FS/GP[1]
MMC0_D0/I2S0_DX/GP[2]
MMC0_D1/I2S0_RX/GP[3]
MMC0_D2/GP[4]
MMC0_D3/GP[5]
MODE 0
00
(Reset Default)
MMC0_CLK
MMC0_CMD
MMC0_D0
MMC0_D1
MMC0_D2
MMC0_D3
MODE 1
01
I2S0_CLK
I2S0_FS
I2S0_DX
I2S0_RX
GP[4]
GP[5]
MODE 2
10
GP[0]
GP[1]
GP[2]
GP[3]
GP[4]
GP[5]
(1)
The pin names with PDINHIBR1 register bit field references can have the pulldown register enabled or disabled via this register.
3.7.1.4
EMIF EM_A[20:15] and GP[26:21] Pin Multiplexing [EBSR.Axx_MODE bits]
The EMIF Address and GPIO signal muxing is determined by the value of the A20_MODE, A19_MODE,
A18_MODE, A17_MODE, A16_MODE, and A15_MODE bit fields in the External Bus Selection Register
(EBSR) register. For more details on the actual pin functions, see Table 3-9 .
Table 3-9. EM_A[20:16] and GP[26:21] Pin Multiplexing
EM_A[15]/GP[21]
EM_A[16]/GP[22]
EM_A[17]/GP[23]
EM_A[18]/GP[24]
EM_A[19]/GP[25]
EM_A[20]/GP[26]
PIN NAME
0
EM_A[15]
EM_A[16]
EM_A[17]
EM_A[18]
EM_A[19]
EM_A[20]
Axx_MODE BIT
1
GP[21]
GP[22]
GP[23]
GP[24]
GP[25]
GP[26]
64
Device Configuration
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